In the field of molecular electronics, few materials show as much promise as carbon nanotubes that comprise hollow cylinders of graphite that have a diameter of a few nanometers. Nanotubes can be implemented in electronic devices, such as, for example, diodes, field effect transistors (FETs), and conductive wiring depending on the nanotube characteristics. Nanotubes are unique for their size, shape and physical properties. For example, carbon based nanotubes resemble a hexagonal lattice of carbon rolled into a cylinder.
Besides exhibiting intriguing quantum behaviors even at room temperature, nanotubes exhibit at least two important characteristics; a nanotube can be either metallic or semiconducting depending on its chirality, i.e., conformational geometry. Metallic nanotubes can carry an extremely large current density with constant resistivity. Semiconducting nanotubes can be electrically switched “on” or “off” as field effect transistors (FETs). These characteristics point to nanotubes as excellent materials for making nanometer sized semiconductor circuits.
Carbon based nanotubes are thus becoming strategically important for post-scaling of conventional semiconductor technologies. For example, a conventional CMOS or BiCMOS process requires providing an n-well to place the pFET. A pFET device, like its nFET counterpart, is typically formed with a lateral source-channel-drain arrangement. Drawbacks in such technologies include pFET device performance lagging the nFET due to lower mobility and separation requirements between the nFET and the pFET due to necessary well boundaries.
Additionally, in some dense static random access memory (SRAM) cells, pFET load devices have been formed in polysilicon layers over the SRAM nFET to make the cell size small. However, pFET device performance and process complexities to form the stacked polysilicon pFET are drawbacks in such devices.
In view of the drawbacks mentioned above with prior art semiconductor structures, there is a need to provide a hybrid semiconductor structure including a planar semiconductor device in which a horizontal carbon nanotube transistor has been integrated therein improving the performance of the structure, while shrinking the overall size of the structure.